xilinx fpga Search Results


fpga  (Xilinx Inc)
86
Xilinx Inc fpga
Diagram of double-scattering Compton camera consisting of three CZT detectors (96 channels), pre-processing analog <t>circuits,</t> <t>ADCs,</t> and <t>FPGA</t> functions
Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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xc6slx75  (Xilinx Inc)
86
Xilinx Inc xc6slx75
Diagram of double-scattering Compton camera consisting of three CZT detectors (96 channels), pre-processing analog <t>circuits,</t> <t>ADCs,</t> and <t>FPGA</t> functions
Xc6slx75, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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xilinx zcu104 fpga platform  (Xilinx Inc)
86
Xilinx Inc xilinx zcu104 fpga platform
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Xilinx Zcu104 Fpga Platform, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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xilinx zynq 7020 fpga  (Xilinx Inc)
86
Xilinx Inc xilinx zynq 7020 fpga
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Xilinx Zynq 7020 Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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processing architecture adopts fpga  (Xilinx Inc)
86
Xilinx Inc processing architecture adopts fpga
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Processing Architecture Adopts Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/product/xilinx+fpga/adopts+architecture+fpga+processing/pm42281068-602-10-14
Average 86 stars, based on 1 article reviews
processing architecture adopts fpga - by Bioz Stars, 2026-09
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artix 7 xc7a200t fpga implementation  (Xilinx Inc)
86
Xilinx Inc artix 7 xc7a200t fpga implementation
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Artix 7 Xc7a200t Fpga Implementation, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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xc7a35tcsg324 fpga hardware platform  (Xilinx Inc)
86
Xilinx Inc xc7a35tcsg324 fpga hardware platform
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Xc7a35tcsg324 Fpga Hardware Platform, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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kintex 410 t fpga  (Xilinx Inc)
86
Xilinx Inc kintex 410 t fpga
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Kintex 410 T Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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amd xilinx virtex 6 sx475t fpga  (Xilinx Inc)
86
Xilinx Inc amd xilinx virtex 6 sx475t fpga
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Amd Xilinx Virtex 6 Sx475t Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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xilinx kintex 7 325t fpga  (Xilinx Inc)
86
Xilinx Inc xilinx kintex 7 325t fpga
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Xilinx Kintex 7 325t Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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xilinx virtex 6 fpga  (Xilinx Inc)
86
Xilinx Inc xilinx virtex 6 fpga
SNN architecture and TTFS encoding module implemented on <t>FPGA</t> (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .
Xilinx Virtex 6 Fpga, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 86/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
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Image Search Results


Diagram of double-scattering Compton camera consisting of three CZT detectors (96 channels), pre-processing analog circuits, ADCs, and FPGA functions

Journal: Nuclear Medicine and Molecular Imaging

Article Title: FPGA-Based Interface of Digital DAQ System for Double-Scattering Compton Camera

doi: 10.1007/s13139-018-0551-8

Figure Lengend Snippet: Diagram of double-scattering Compton camera consisting of three CZT detectors (96 channels), pre-processing analog circuits, ADCs, and FPGA functions

Article Snippet: The FPGA plays three main roles: controlling the interface between the ADCs and the FPGA, digital signal processing to extract the detection information (energy and detection locations) from the coincident measurements, and providing the transfer interface between the FPGA and the PC. fig ft0 fig mode=article f1 fig/graphic|fig/alternatives/graphic mode="anchored" m1 Open in a separate window Fig. 3 caption a7 Digital data acquisition board of double-scattering Compton camera consisting of two main components, 12 ADCs (ADS-5281, Texas Instruments) and a FPGA (Artix7-200T, Xilinx) Interface between ADCs and FPGA The following is a description of the setting we developed for the interface between the ADCs and the FPGA.

Techniques:

Digital data acquisition board of double-scattering Compton camera consisting of two main components, 12 ADCs (ADS-5281, Texas Instruments) and a FPGA (Artix7-200T, Xilinx)

Journal: Nuclear Medicine and Molecular Imaging

Article Title: FPGA-Based Interface of Digital DAQ System for Double-Scattering Compton Camera

doi: 10.1007/s13139-018-0551-8

Figure Lengend Snippet: Digital data acquisition board of double-scattering Compton camera consisting of two main components, 12 ADCs (ADS-5281, Texas Instruments) and a FPGA (Artix7-200T, Xilinx)

Article Snippet: The FPGA plays three main roles: controlling the interface between the ADCs and the FPGA, digital signal processing to extract the detection information (energy and detection locations) from the coincident measurements, and providing the transfer interface between the FPGA and the PC. fig ft0 fig mode=article f1 fig/graphic|fig/alternatives/graphic mode="anchored" m1 Open in a separate window Fig. 3 caption a7 Digital data acquisition board of double-scattering Compton camera consisting of two main components, 12 ADCs (ADS-5281, Texas Instruments) and a FPGA (Artix7-200T, Xilinx) Interface between ADCs and FPGA The following is a description of the setting we developed for the interface between the ADCs and the FPGA.

Techniques:

Sync calibration of interface between ADCs and FPGA with two test patterns, Deskew and MSB

Journal: Nuclear Medicine and Molecular Imaging

Article Title: FPGA-Based Interface of Digital DAQ System for Double-Scattering Compton Camera

doi: 10.1007/s13139-018-0551-8

Figure Lengend Snippet: Sync calibration of interface between ADCs and FPGA with two test patterns, Deskew and MSB

Article Snippet: The FPGA plays three main roles: controlling the interface between the ADCs and the FPGA, digital signal processing to extract the detection information (energy and detection locations) from the coincident measurements, and providing the transfer interface between the FPGA and the PC. fig ft0 fig mode=article f1 fig/graphic|fig/alternatives/graphic mode="anchored" m1 Open in a separate window Fig. 3 caption a7 Digital data acquisition board of double-scattering Compton camera consisting of two main components, 12 ADCs (ADS-5281, Texas Instruments) and a FPGA (Artix7-200T, Xilinx) Interface between ADCs and FPGA The following is a description of the setting we developed for the interface between the ADCs and the FPGA.

Techniques:

SNN architecture and TTFS encoding module implemented on FPGA (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .

Journal: iScience

Article Title: System-level FPGA validation of a trainable and robust multiplier-free spiking neural network

doi: 10.1016/j.isci.2026.115985

Figure Lengend Snippet: SNN architecture and TTFS encoding module implemented on FPGA (A) Overall FPGA-based implementation of the SNN system. An on-chip controller orchestrates the execution of inference and training submodules under external commands. Dashed arrows denote control signals, while solid arrows indicate data flow between functional modules. (B) Hardware structure of the TTFS encoder. Pixel inputs are compared with a global countdown counter to generate spike signals, and a range decoder extracts the relative spike timing to produce positional outputs Pos i .

Article Snippet: By implementing a sensitive-noise threshold (SNT) mechanism and a limited remote supervised method (LReSuMe) on a Xilinx ZCU104 FPGA platform, the proposed design achieves high throughput, low power consumption, and preserved robustness to the noise.

Techniques: Control, Functional Assay

FPGA-based implementation of the neuron computation, weight storage, decay, and training modules (A) Neuron computation module implemented on FPGA, illustrating the datapath from TTFS-encoded spike trains to the final output score. The module consists of an adder tree for spike accumulation, a membrane potential updating unit, and an output layer that detects threshold crossings based on SNT and updates the output score accordingly. (B) Organization of 4,000 synaptic weights across 20 on-chip block RAMs (BRAMs). Each BRAM stores weights associated with a single output neuron, enabling parallel access to all corresponding synaptic weights during inference and training by fixing the neuron address. (C) Multiplier-free circuit for realizing a fixed decay coefficient D = 0.75 using a shift-and-add structure. Partial results generated by binary shifts are combined through addition to obtain the scaled output, representing a standard hardware-efficient implementation for constant multiplication in FPGA designs. (D) FPGA-based training module implementing fixed-point weight updates using an LReSuMe-based learning rule. The module includes a shift-and-add learning multiplication unit and a zero replacement unit (ZRU) to mitigate quantization-induced null updates.

Journal: iScience

Article Title: System-level FPGA validation of a trainable and robust multiplier-free spiking neural network

doi: 10.1016/j.isci.2026.115985

Figure Lengend Snippet: FPGA-based implementation of the neuron computation, weight storage, decay, and training modules (A) Neuron computation module implemented on FPGA, illustrating the datapath from TTFS-encoded spike trains to the final output score. The module consists of an adder tree for spike accumulation, a membrane potential updating unit, and an output layer that detects threshold crossings based on SNT and updates the output score accordingly. (B) Organization of 4,000 synaptic weights across 20 on-chip block RAMs (BRAMs). Each BRAM stores weights associated with a single output neuron, enabling parallel access to all corresponding synaptic weights during inference and training by fixing the neuron address. (C) Multiplier-free circuit for realizing a fixed decay coefficient D = 0.75 using a shift-and-add structure. Partial results generated by binary shifts are combined through addition to obtain the scaled output, representing a standard hardware-efficient implementation for constant multiplication in FPGA designs. (D) FPGA-based training module implementing fixed-point weight updates using an LReSuMe-based learning rule. The module includes a shift-and-add learning multiplication unit and a zero replacement unit (ZRU) to mitigate quantization-induced null updates.

Article Snippet: By implementing a sensitive-noise threshold (SNT) mechanism and a limited remote supervised method (LReSuMe) on a Xilinx ZCU104 FPGA platform, the proposed design achieves high throughput, low power consumption, and preserved robustness to the noise.

Techniques: Membrane, Blocking Assay, Generated

Noise modeling, training accuracy comparison, and fixed-point saturation behavior (A) Illustration of impulse noise modeling in the MNIST dataset. From left to right: original image, image corrupted with random impulse noise (random positions and random values), and image corrupted with impulse noise (random positions with pixel values replaced by either 0 or 255). (B) Training accuracy comparison among six different network configurations and quantization settings on the clean MNIST training dataset. Accuracy is reported per 100-image chunk. (C) Evolution of final output scores under different fixed-point formats during training. Results are shown for FPGA Q6.10 (left) and Q6.26 (right) implementations. The x axis denotes the uniformly sampled time step index selected from the first 180 training chunks of the hardware simulation, and the y axis represents the final output score S o j . At each sampled time step, the maximum, mean, and standard deviation of S o j across all output neurons are computed and visualized.

Journal: iScience

Article Title: System-level FPGA validation of a trainable and robust multiplier-free spiking neural network

doi: 10.1016/j.isci.2026.115985

Figure Lengend Snippet: Noise modeling, training accuracy comparison, and fixed-point saturation behavior (A) Illustration of impulse noise modeling in the MNIST dataset. From left to right: original image, image corrupted with random impulse noise (random positions and random values), and image corrupted with impulse noise (random positions with pixel values replaced by either 0 or 255). (B) Training accuracy comparison among six different network configurations and quantization settings on the clean MNIST training dataset. Accuracy is reported per 100-image chunk. (C) Evolution of final output scores under different fixed-point formats during training. Results are shown for FPGA Q6.10 (left) and Q6.26 (right) implementations. The x axis denotes the uniformly sampled time step index selected from the first 180 training chunks of the hardware simulation, and the y axis represents the final output score S o j . At each sampled time step, the maximum, mean, and standard deviation of S o j across all output neurons are computed and visualized.

Article Snippet: By implementing a sensitive-noise threshold (SNT) mechanism and a limited remote supervised method (LReSuMe) on a Xilinx ZCU104 FPGA platform, the proposed design achieves high throughput, low power consumption, and preserved robustness to the noise.

Techniques: Comparison, Standard Deviation